![]() RTL Design – combinational logic – Sequential circuit – Operators – Introduction to Packages – Subprograms – Test bench. ![]() ![]() UNIT IV ASYNCHRONOUS SEQUENTIAL CIRCUITS AND PROGRAMMABILITY LOGIC DEVICESĪsynchronous sequential logic circuits-Transition tability, flow tability-race conditions, hazards &errors in digital circuits analysis of asynchronous sequential logic circuits introduction to Programmability Logic Devices: PROM – PLA –PAL, CPLD-FPGA. Sequential logic- SR, JK, D and T flip flops - level triggering and edge triggering - counters - asynchronous and synchronous type - Modulo counters - Shift registers - design of synchronous sequential circuits – Moore and Melay models- Counters, state diagram state reduction state assignment. Review of number systems, binary codes, error detection and correction codes (Parity and Hamming code) - Digital Logic Families -comparison of RTL, DTL, TTL, ECL and MOS families -operation, characteristics of digital logic family.Ĭombinational logic - representation of logic functions-SOP and POS forms, K-map representations - minimization using K maps - simplification and implementation of combinational logic – multiplexers and de multiplexers - code converters, adders, subtractors, Encoders and Decoders. ![]() UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES
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